International Journal of Information Technology & Computer Science ( IJITCS )
A register that goes through a sequence of distinct states upon the application of a sequence of input pulses is called a counter. Counters which count upward from zero to maximum are called binary counter. In this counter the ability of faults are available . The characteristics of these types of faults render them undetectable by standard test strategies. The detection of intermittent faults requires the use of Concurrent Error Detection (CED) technique, which continuously monitors the operation of circuits and compares them with some known reference. This is achieved by incorporating some form of redundancy into the system . One method of implementing CED in VLSI circuit is through the use of information redundancy. This paper investigates the use of information redundancy into unchecked system as a mean of incorporating CED into a self-checking binary counter .
: binary counter, Self checking, Concurrent Error Detection, Information Redundancy
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