In some communication systems, data is transmitted with an accompanying clock and in some systems data is transmitted without an accompanying clock. In either case, it is important to recover clock at the receiver. Clock is used to sample the data to convert it from analog to digital form. Since the clock is required to sample the data at receiver, it needs to match the clock used at the transmitter for faithful recovery of the information transmitted. This paper discusses some in use phase detection techniques, used to synchronize data and clock at the receiver for appropriate sampling of the data. Discussions along with simulations for the classic bang-bang (alexander) phase detector are performed. Based on analysis and requirements, alternative designs for phase detectors are developed and supported with MATLAB simulations and circuit diagrams. These phase detectors are to be followed by appropriate circuitry such as the PLL (phase locked loop) to adjust the phase of the clock and data so that they are synchronized, where the phase detector component is what will be emphasized on.
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. Data presentation- Concept Creation and Design of a Parameterizable, fast-locking 65 nm CMOS CDR-PLL for Gigabit Serial Chip-to-Chip Communication in Mobile Devices Milan Forcan By Prof. Dr.-Ing. Klaus Solbach, University of Duisburg-Essen, Department of Microwave and RF-Technology